1. Field of the Invention
The present invention relates to a high swing interface output stage integrated circuit for interfacing a device with a data bus which operates at voltages outside the power supply voltage of the interface circuit and which may be shared by other devices which may operate at power supply voltages outside the power supply voltage of the interface circuit. The invention also relates to a method for providing such a high swing interface output stage integrated circuit.
2. Prior Art
Output stage interface circuits for interfacing devices namely, data communications devices, for example, computers with a data bus operating under transmission standards such as RS485, RS422, R5232 and CANbus are known. Such standards operate at a relatively wide range of output terminal voltages; for example, RF485, specifics operation, at an output terminal voltage up to +12 volts and down as low as -7 volts, and indeed some transmission standards operate at voltage ranges greater than these.
A conventional interface circuit for interfacing a device with a data bus comprises a CMOS circuit, of the type illustrated in FIG. 1. Supply rails V.sub.dd and GND of the interface circuit of FIG. 1 are connected to a bus output terminal OUT through a PMOS FET P1 and an NMOS FET N1, respectively. Input signals on the gates of the MOS FETS P1 and P2 alternately operate the MOS FETS for determining the respective high and low states of the output terminal OUT in response to high and low states of input signals. While such an interface circuit is adequate for interfacing a device with a data bus provided the data bus is operating at an output terminal voltage within the power supply voltage V.sub.dd of the interface circuit, these interface circuits are unsuitable where the output terminal voltage of the data bus is outside the supply voltage of the interface circuit. On the output terminal voltage of the interface circuit being driven outside the supply voltage, the source and drain of the relevant MOS FET P1 or N1 reverse, and a parasitic diode Dp between the well and the drain of that MOS FET P1 or N1, provides a conductive path through the MOS FET P1 or N1 between the output terminal OUT and the corresponding supply rail V.sub.DD or GND. This causes either sinking of current from the data bus into the interface circuit, or sourcing of current from the interface circuit into the data bus, either of which causes corruption of data on the data bus, and may cause damage to the interface circuit.
Since many data communications devices, in particular, laptop computers operate at relatively low voltage power supplies, for example, at or below 5 volts, and in many cases, as low as 3 volts, there is a need for an interface output stage for interfacing such low voltage devices with a data bus operating at output terminal voltages well outside the range of the power supply of the low voltage device. Additionally, since many transmission standards require a relatively high differential output swing voltage, such an interface output stage integrated circuit must also be capable of providing a relatively high differential output swing voltage, even when operating at relatively low voltages, such as 3 volts. The transmission standard RS485 requires a differential output voltage of 1.5 volts to be developed across a differential load resistor of 54 ohms, while the RS422 transmission standard requires an output terminal voltage of 2 volts (single-ended) developed across a load resistor of 100 ohms.
U.S. Pat. No. 5,414,314 discloses an interface output stage integrated circuit which while operating at a relatively low supply voltage, can develop a relatively high swing output terminal voltage. The circuit of the prior art U.S. specification also presents a high impedance to the output terminal in the event of the output terminal being driven to a voltage outside the supply voltage of the circuit when the circuit is powered and not active. The circuit of U.S. Pat. No. 5,414,314 achieves this by having three P channel devices, namely, three PMOS FETS formed in a common well on the substrate of the integrated circuit, and three N channel devices, namely, three NMOS FETS formed in another common well on the substrate. Two of the PMOS FETS and two of the NMOS FETS are coupled in series between the output terminal and the supply voltage rail and the ground rail, respectively, of the output stage. The third NMOS FET and the third PMOS FET are coupled between the common connection of the other two corresponding first and second FETS and the gates of the second corresponding FETS. The common connection of each set of three FETS is connected to the corresponding common well of the three FETS. The third FETS hold the second FETS off in the event of the output terminal voltage being driven above or below the voltages on the supply and ground rails when the circuit is powered up and inactive, for providing high impedance between the output terminal and the respective supply and ground rails.
While the circuit of U.S. Pat. No. 5,414,314 permits the output terminal to be driven by the bus to a voltage above or below the supply voltage of the output stage when the output stage is powered up and inactive, it suffers from a number of disadvantages. Firstly, it is formed by a CMOS process, which needless to say, increases the number of process steps in the fabrication of the integrated circuit. Secondly, the circuit of the U.S. prior art specification tends to be temperature dependent. The differential output voltage of the circuit falls off relatively rapidly with a rise in temperature of the output stage. Thus, in order to meet a particular differential output voltage at high temperatures, the PMOS and NMOS FETS of the prior art circuit must be of relatively large size. This requires the provision of a relatively expensive die, and furthermore, the large size FETS are redundant at lower temperatures. This is a significant disadvantage.
There is therefore a need for an interface output stage integrated circuit for interfacing a device with a data bus, which is suitable for operating at a relatively low supply voltage, and is capable of developing a relatively high swing output voltage. The interface circuit should prevent excessive sinking of current from the data bus, or excessive sourcing of current from the circuit to the data bus in the event of the output terminal being driven to a voltage outside the supply voltage of the circuit. Additionally, the interface circuit should overcome the problems of known prior art devices, and in particular the number of processing steps required in the fabrication of the integrated circuit should be minimised, and the interface circuit should be relatively temperature independent, and should be relatively inexpensive to fabricate.